Communication semiconductor integrated circuit device and a wireless communication system

ABSTRACT

In one embodiment, a PLL circuit is provided with a plurality of pull-in operation modes for pulling a voltage across a filter capacitor (C 1 , C 2 ) in a lock-up voltage, and with a register (CRG) for designating one of the plurality of pull-in operation modes. The pull-in operation is performed in accordance with a setting value in the register.

The present invention relates to techniques effective for application toa phase locked loop (PLL) circuit with a voltage controlled oscillator(VCO). More particularly, the invention relates to techniques effectivefor application to a PLL circuit of a mobile communication apparatussuch as a portable phone capable of transmitting/receiving signals in aplurality of frequency bands, the PLL circuit generating an oscillationsignal having a predetermined frequency to be synthesized with areception/transmission signal, and to a high frequency semi-conductorintegrated circuit device and a wireless communication system using thePLL circuit.

A portable phone has a high frequency semiconductor integrated circuitdevice (hereinafter called a high frequency LSI) having a PLL circuitoperating as a local oscillator for generating an oscillation signal ofa predetermined frequency to be synthesized with a transmission signalto modulate it and with a reception signal to demodulate it.

A dual band type portable phone is known which can process signals intwo frequency bands such as Global System for Mobil Communication (GSM)in the frequency band from 880 to 915 MHz and Digital Celluar System(DCS) in the frequency band from 1710 to 1785 MHz. There is a PLLcircuit for such a dual band type portable phone which can processsignals in the two frequency bands by changing the frequency of the PLLcircuit.

During the standby state, the operation of the PLL circuit of a portablephone is stopped. The PLL circuit of a dual band type portable phone isrequired to change the frequency in accordance with the frequency bandof a transmission/reception signal. During this frequency change, somePLL circuits are required to stop their operations. The PLL circuit oncestopped is required to start again when the transmission resumes.According to a conventional general method of gradually making thecontrol voltage Vc of VCO constituting the PLL circuit change near to alock-up voltage, the lock-up time of the PLL circuit fortransmission/reception in the higher frequency band is inherently longerthan the lock-up time for transmission/reception in the lower frequencyband.

To solve this problem, a lock-up method for a dual band type has beenproposed. With this method, as shown in FIG. 3B, a current source forquickly charging up the capacitor of a loop filter for generating acontrol voltage Vc of VCO is provided to set the control voltage Vc onceto a power supply voltage Vcc and then gradually lower it fortransmission/reception in the higher frequency band.

This method is, however, associated with a possibility of a so-calledimage lock. Namely, if the frequency range which VCO can oscillate isbroad, PLL locks at a frequency higher than a desired frequency asindicated by a broken line in FIG. 3B. A triple band type portable phonecan process signals in GSM and DCS and in addition, for example, inPersonal Communication System (PCS) in the frequency band from 1850 to1915 MHz. In this case, it is necessary to set the frequency band, whichVCO of the high frequency LSI for such a triple band type portable phonecan process, broader than that of the dual band type of GSM and DCS.

It can be considered that a high frequency LSI for a portable phone isrequired to be able to process signals in a large number of frequencybands in the future. A PLL circuit for a multi band type high frequencyLSI requires a higher speed lock-up method than the above-describedmethod. A general purpose high frequency LSI is desired which can beapplied to all of dual band, triple band and single band portablephones. If there is such a general purpose high frequency LSI, portablephone manufacturers can utilize conventional hardware and softwaredesign resources. A system for a new high frequency LSI is not requiredto be designed again so that the development cost can be reduced.

The present inventors have studied methods of generating an intermediatefrequency (hereinafter called an IF signal) prior to developments of ahigh frequency LSI compatible with three communication methods GSM, DCSand PCS. If the conventional method of changing the frequency of an IFsignal of a high frequency LSI compatible with two communication methodsGSM and DCS is incorporated, it is necessary to broaden the frequencyrange of the IF signal which VCO can oscillate or to selectively use twoor three VCO's. This considerably increases the manufacture cost. Ifthree IF signals are used, it is necessary to use three filters calledharmonic filters for cutting harmonic components of the three IFsignals. This increases the circuit area and chip size.

An object of the present invention is to provide a communicationsemiconductor integrated circuit device (high frequency LSI) having aPLL circuit with a plurality of pull-in modes capable of entering alock-up state in a short time without an image lock by performing thepull-in operation in the pull-in mode suitable for the frequency band.

Another object of the present invention is to provide a communicationsemiconductor integrated circuit device being able to utilizeconventional design resources and having a PLL circuit with a pluralityof pull-in modes performing a pull-in operation by selecting the pull-inmode suitable for the system.

Preferably, another object of the present invention is to provide amethod of setting the frequency of an IF signal, the method beingsuitable for a high frequency LSI capable of processing signals by aplurality of communication methods such as GSM, DCS and PCS.

Preferably, another object of the invention is to provide a highfrequency LSI capable of processing signals by a plurality ofcommunication methods such as GSM, DCS and PCS, in which a main portionof an oscillation circuit for generating an IF signal can be formed on asingle semiconductor chip, the number of necessary filters can bereduced, and the circuit area can be reduced.

According to one aspect of the present invention, a PLL circuit isprovided with a plurality of pull-in operation modes for pulling thevoltage across the filter capacitor in a lock-up voltage, and with aregister for designating one of the plurality of pull-in operationmodes, and the pull-in operation is performed in accordance with asetting value in the register. Preferably, at last one of the pluralityof pull-in operation modes is an operation mode of starting the pull-inoperation at a predetermined initial voltage lower than the lock-upvoltage. Preferably, at last one of the plurality of pull-in operationmodes is an operation mode of raising the voltage across the filtercapacitor to a predetermined voltage higher than the lock-up voltage andthereafter gradually lowering the voltage across the filter capacitor.

According to the above-described aspect, one of the plurality of pull-inoperation modes can be selected by using the register. Accordingly, thePLL circuit can be locked up in a short time without an image lock.Since the pull-in operation modes same as the conventional modes areprovided, conventional design resources can be utilized.

Preferably, the PLL circuit is structured so that it can select one of aplurality of levels as the initial voltage and a second register isprovided for designating one of the plurality of levels. Since theinitial voltage can be selected in accordance with a setting value inthe second register, the lock-up can be realized at an optimum pull-inspeed in accordance with the system and frequency band to be used.

According to another aspect of the present invention, in a wirelesscommunication system capable of transmission/reception in conformitywith a communication method using two or more frequency bands includingat least a GSM method using a 900 MHz frequency band, the same frequencyof an intermediate frequency signal to be modulated by transmission datais used for the two or more frequency bands. Since only one oscillatorcircuit is used for generating the intermediate frequency signal, a onechip communication semiconductor integrated circuit device having amodulation circuit can be realized. Since the oscillation frequency ofthe oscillation circuit is not necessary to be changed even if thefrequency band to be used is changed, it is possible to generate anoscillation signal having a high precision frequency.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a charge pump constituting a PLL circuitaccording to an embodiment of the invention.

FIGS. 2A and 2B are an equivalent circuit of the charge pump in a firstpull-in mode (normal pull-in mode) of the PLL circuit shown in FIG. 1,and a timing chart illustrating the first pull-in mode.

FIGS. 3A and 3B are an equivalent circuit of the charge pump in a secondpull-in mode (down-sweep pull-in mode) of the PLL circuit shown in FIG.1, and a timing chart illustrating the second pull-in mode.

FIGS. 4A and 4B are an equivalent circuit of the charge pump in a thirdpull-in mode (up-sweep pull-in mode) of the PLL circuit shown in FIG. 1,and a timing chart illustrating the third pull-in mode.

FIGS. 5A and 5B are an equivalent circuit of the charge pump in a fourthpull-in mode (up-sweep ultra high speed pull-in mode) of the PLL circuitshown in FIG. 1, and a timing chart illustrating the fourth pull-inmode.

FIGS. 6A and 6B are a circuit diagram of a charge pump constituting aPLL circuit and a timing chart illustrating the operation, according toanother embodiment of the invention.

FIG. 7 is a block diagram showing an example of the structure of aportable phone as one example of a wireless communication system,according to another embodiment of the invention.

FIG. 8 is a block diagram showing an example of the structure of atransmitter unit of a portable phone as one example of a wirelesscommunication system, according to another embodiment of the invention.

DESCRIPTION OF THE EMBODIMENTS

Embodiments of the invention will be described with reference to theaccompanying drawings.

FIG. 1 shows a charge pump constituting a PLL circuit capable ofperforming a pull-in operation in a plurality of pull-in modes,according to an embodiment of the invention. In FIG. 1, referencenumeral 10 represents a charge pump, and reference numeral 20 representsa loop filter. A charge voltage Vc of the loop filer 20 is output as acontrol voltage for a VCO (not shown).

As shown in FIG. 1, the charge pump 10 of this embodiment has: a switchSW1 which is turned on and off by an up signal UP supplied from a phasedetecting circuit (not shown); a switch SW2 which is turned on and offby a down signal DOWN supplied from the phase detecting circuit;constant current sources I1 and I2 serially connected to the switchesSW1 and SW2; and a switch SW0 connected between a charge/discharge nodeN1 and ground point. The switches SW1 and SW2 are turned on and off bythe up signal Up and down signal DOWN supplied from the phase detectingcircuit so that capacitors C1 and C2 of the loop filter 20 are chargedup and down to make constant the control voltage Vc under the conditionthat the PLL circuit is locked. A switch SW0 resets the voltage Vc ofthe loop filter 20 to a zero voltage when the operation of the PLLcircuit stops.

In order to speed up the PLL circuit pull-in operation, the charge pump10 of this embodiment has also: a switch SW3 and a constant currentsource I3; a switch SW4 and a constant current source I4; a switch SW5and a constant current source I5; a switch SW6 and a constant currentsource I6, respectively connected between the power source voltage Vccand charge/discharge node N1; a switch SW7 and a constant current sourceI7; and a switch SW8 and a constant current source I8, respectivelyconnected between the charge/discharge node N1 and ground point.

Of the constant current sources I3 to I8, the constant current source I3is a current source for flowing a reference current and is used for apull-in operation at a relatively low frequency. The constant currentsource I4 is used for charging up the charge/discharge node N1 to thepower source voltage Vcc. The current I4 is much larger than the currentI3, i.e., I4>>I3. The constant current source I5 flows a current of a×I3(I5<I4) where a>1, the constant current source I6 flows a current ofa×I1, and the constant current source I7 flows a current of a×I2. Theconstant current I8 is a current source used for charging down after thecharge/discharge node N1 is once charged up to the power source voltageVcc by the constant current source I4 to change the frequency near to atarget frequency, and flows a current, for example, approximately equalto the constant current source I3.

In the PLL circuit of this embodiment, the following four pull-in modesare possible under the control of the switches SW3 to SW8 during theoperation of the PLL circuit.

A first pull-in mode is a normal pull-in mode using only the constantcurrent source I3. FIG. 2A shows the equivalent circuit in this mode,and FIG. 2B is a timing chart illustrating this mode. In this mode, whena start-up signal TXON rises, the switch SW0 is turned off and theswitch SW3 is turned on by a control signal PPON3. Therefore, thevoltage Vc at the node N1 rises along a slope determined by the timeconstant of the loop filter 20 and the current value of the constantcurrent source I3. After the voltage Vc reaches a voltage sufficient forthe PLL control, the loop is controlled by I1 and I2 and the voltage Vcis fixed to the lock-in voltage. A time period t1 from the PLL start-upto when the voltage Vc is fixed, is a lock-up time.

A second pull-in mode is a down-sweep pull-in mode using the constantcurrent sources I4 and I8. FIG. 3A shows the equivalent circuit in thismode, and FIG. 3B is a timing chart illustrating this mode. In thismode, first the switch SW4 is turned on for a time period t2 by acontrol signal PPON4. After the loop filter 20 is charged up once to thepower source voltage Vcc by the constant current source I4, the switchSW4 is turned off. Then, the switch SW8 is turned on by a control signalPPON8 and the node N1 is charged down by the constant current I8 to thelock-up voltage.

A third pull-in mode is an up-sweep pull-in mode using the constantcurrent sources I3 and I5. FIG. 4A shows the equivalent circuit in thismode, and FIG. 4B is a timing chart illustrating this mode. In thismode, first the switches SW3 and SW5 are turned on for a time period t4by control signals PPON3 and PPON5. After the loop filter 20 is chargedup to a voltage slightly lower than the target voltage by the constantcurrent source I5, the switch SW5 is turned off and the switch SW3 ismaintained on by the control signal PPON3. Therefore, the loop filter 20is gradually charged up by the constant current source I3 to reach alock-up voltage. In this mode, therefore, the pull-in operation can beperformed at a higher speed than the first mode (normal mode), and animage lock which is likely to occur in the second mode can be avoided.The PLL loop operation state (closed loop bandwidth) in the lock-instate is the same as the normal mode.

A fourth pull-in mode is an up-sweep ultra high speed pull-in mode usingthe constant current sources I5, I6 and I7. FIG. 5A shows the equivalentcircuit in this mode, and FIG. 5B is a timing chart illustrating thismode. In this mode, first the switch SW5 is turned on by a controlsignal PPON0 so that the loop filter 20 is charged up to the powersource voltage Vcc by the constant current sources I3 and I5. At thistime, the constant current sources I6 and I7 are controlled by the upsignal UP and down signal DOWN same as the constant current sources Iland I2 and the control signal PPON0.

Therefore, the loop filter 20 is charged up substantially by thecurrents of the constant current sources I3 and I5, i.e., (a+1)×I3. Evenif the sweep-up is performed by the current (a+1)×I3 larger than I3 inthe normal mode, the current of the constant current sources I1 and I2controlled by the signals supplied from the phase detecting circuit atthe preceding stage is multiplied by (a+1), so that the control of thePLL loop operates normally and the lock-in is possible.

The closed loop bandwidth in the lock-in state is proportional to thecurrent of the constant current sources I1 and I2 controlled by signalssupplied from the phase detecting circuit. Therefore, if the current ofthe constant current sources I1 and I2 is maintained large, noisescannot be eliminated sufficiently. However, in the fourth mode of thePLL circuit of this embodiment, immediately after the lock-in, theswitches SW6 and SW7 together with the switch SW5 are turned off by thecontrol signal PPON0. Therefore, the closed loop bandwidth in thelock-in state can be made same as that of the other modes.

FIGS. 6A and 6B are a circuit diagram of a PLL circuit and a timingchart illustrating the operation, according to another embodiment of theinvention. In this embodiment, in place of the constant current sourcesI4 to I8 of the charge pump of the above-described embodiment, there isprovided a pre-charge circuit VCP for raising the level of thecharge/discharge node N1 at the start-up time. For example, as shown inFIG. 6A, the pre-charge circuit VCP is constituted of: a switch SW9, aconstant current source I9, diodes D1 and D2 and a resistor R1,respectively connected serially between the power supply voltage Vcc andground point; and a transistor Q1 and a diode D3 respectively connectedserially between the power supply voltage Vcc and charge/discharge nodeN1 of the charge pump. A potential at a connection node N2 between theconstant current source I9 and diode D1 is applied to the base of thetransistor Q1.

In this embodiment, resistors R2, R3, . . . are also provided inparallel to the resistor R1. Switches SW12, SW13, . . . are connected tothe resistors R2, R3., . . . . In FIG. 6A, only the resistors R2 and R3and switches SW12 and SW13 are shown and other resistors and switchesare omitted. In the pre-charge circuit VCP of this embodiment, when theswitch SW9 is turned on by a start-up signal TXON and current flows fromthe constant current source I9, the transistor Q1 turns on so that thepotential at the charge/discharge node N1 of the charge pump 10 risesquickly.

The base-emitter voltage of the transistor Q1 can be considered equal tothe forward voltage of the diode. When the transistor Q1 is turned on,the potential at the charge/discharge node N1 of the charge pump 10 islower than the base potential of the transistor Q1 by a twofold of thediode forward voltage. The base potential of the transistor Q1 is higherthan the potential at a connection node N3 between the resistor R1 anddiode D2 by a twofold of the diode forward voltage. Therefore, as shownin FIG. 6B, the potential at the charge/discharge node N1 of the chargepump 10 is raised quickly after the start-up to the potential at theconnection node N3 between the resistor R1 and diode D2 of thepre-charge circuit VCP, and thereafter, the potential is raised by thecurrent from the constant current source I3. As a result, the potentialreaches the lock-up voltage faster than the case that the pre-chargecircuit VCP is charged up only by the current from the constant currentsource I3. The potential at the connection node N3 is determined by thevalue of the resistor R1 and the current flowing therethrough.

In this embodiment, the resistors R2, R3, . . . are provided in parallelto the resistor R1, and the resistor through which current flows can beselected by the switches SW12, SW13, . . . . Therefore, by controllingthe switches SW12, SW13, . . . , the potential at the node N2, i.e., aninitial voltage at the start-up of the charge pump 10 can be set asdesired. When the transistor Q1 turns on, the collector current of thetransistor Q1 charges the capacitors of the loop filter 20, and when thepotential at the charge/discharge node N1 of the charge pump 10 rises tothe potential at the node N3 of the pre-charge circuit VCP, thetransistor Q1 is automatically turned off. It is therefore sufficienteven if the time period t6 of the high level of the control signal PPONfor the transistor Q1 is relatively short.

In the pull-in mode shown in FIGS. 4A and 4B, it can be considered thatthe initial charge-up by the current of the constant current source I3and the current of a×I3 gives the initial voltage for the charge-up tobe performed continuously by the constant current source I3. Namely, thepre-charge circuit VCP shown in FIG. 6A can be considered as amodification of the embodiment shown in FIGS. 4A and 4B. As a method ofsetting a plurality of initial voltages to the charge pump at the PLLstart-up time, the resistors R1, R2, R3, . . . may be replaced by diodetrains each having the different number of diodes.

Next, the description is directed to the case that a PLL circuit isapplied to a high frequency LSI of a mobile communication system of amulti band type. FIG. 7 shows an example of the detailed structure of ahigh frequency LSI and the outline structure of a mobile communicationsystem, according to another embodiment of the invention.

In FIG. 7, an antenna 100 transmits/receives a radio wave. Referencenumeral 200 represents a high frequency LSI, and reference numeral 110represents a transmission/reception switch (duplexer). A high frequencypower amplifier circuit 120 amplifies a transmission signal. Referencenumeral 130 represents a transmission oscillator TXVCO, and referencenumeral 140 represents a loop filter constituting a transmission sidePLL circuit. A high frequency oscillator RFVCO 150 generates anoscillation signal having a frequency corresponding to a desiredfrequency band. A high frequency filter 160 removes unnecessary radiowaves from a reception signal. A baseband circuit (LSI) 300 converts atransmission signal into I and Q signals and controls the high frequencyLSI 200. Although not specifically limited, in this embodiment, the highfrequency oscillator RFVCO 150 is used in common for the transmissionside circuit and reception side circuit.

The transmission side circuit of the high frequency LSI 200 includes: anoscillator circuit IFVCO 210; a frequency dividing circuit 220; amodulator circuit 230; a frequency dividing circuit 250; a mixer 260; aharmonic filter 242; a phase detecting circuit 270; a charge pump 280; amode control circuit 290; and the like. The oscillator circuit IFVCO 210generates an oscillation signal φIF having an intermediate frequencyFRF, e.g., 320 MHz. The frequency dividing circuit 220 frequency-dividesthe oscillation signal φIF generated by the oscillation circuit 210 andgenerates a carrier having a frequency of, e.g., 80 MHz. The modulatorcircuit 230 quadrature-modulates the carrier output from the frequencydividing circuit 220 by using the I and Q signals supplied from thebaseband circuit 300. The frequency dividing circuit 250frequency-divides a signal φRF′ supplied from the high frequencyoscillator 150. The mixer 260 synthesizes the signal φRF′frequency-divided by the frequency dividing circuit 250 and atransmission signal φTX fed back from the transmission oscillator TXVCO130 to generate a signal φmix having a frequency corresponding to thefrequency difference between the two signals. The harmonic filter 242cuts the harmonic components of a signal leaked from the mixer 260. Thephase detecting circuit 270 detects a phase difference between thesignal supplied from the mixer 260 and the modulation signal suppliedfrom the modulator circuit 230. The charge pump 280 is controlled bysignals UP and DOWN output from the phase detecting circuit 270.

The reception side circuit includes; a low noise amplifier 310 foramplifying a reception signal; a demodulator circuit 320 for performinga demodulation operation by synthesizing the reception signal and theoscillation signal φRF of the high frequency oscillator 150frequency-divided by the frequency dividing circuit 250; a programmablegain amplifier 330 for amplifying a demodulated signal and outputting itto the baseband circuit 300.

In this embodiment, the circuit having the structure shown in FIG. 1 isused for the charge pump 280 and loop filter 140. The transmission sidePLL circuit TXPLL generally called an offset PLL for frequencyconversion is constituted of the charge pump 280, phase detectingcircuit 270, loop filter 140, transmission oscillator TXVCO 130 andmixer 260. In the mobile communication system of a multi band type, thetransmission frequency is changed with the frequency band to be used, bychanging the oscillation frequency FRF of the high frequency oscillator150, for example, in response to a command from the baseband circuit300.

The mode control circuit 290 has a control register CRG. Values are setin this control register CRG in accordance with a signal from thebaseband circuit 300. More specifically, the baseband circuit 300supplies the high frequency LSI 200 with a clock signal CLK forsynchronization, a data signal SDATA, and a load enable signal LEN as acontrol signal. When the load enable signal LEN of an effective level isasserted, the mode control circuit 290 sequentially captures the datasignal SDATA sent from the baseband circuit 300 synchronously with theclock signal CLK and sets it to the control register GRG. Although notspecifically limited, the data signal SDATA is sent serially. Thebaseband circuit 300 is made of a microprocessor and the like.

Although not specifically limited, in this embodiment, the controlregister CRG has two bits of PLL pull-in mode selection bits PP0 and PP1and three bits of pulse width designation bits TP0 to TP2 fordesignating the pulse width of each signal PPON, i.e., the on-time ofeach switch which controls on-off of each of the switches SW3 to SW8 ofthe charge pump 10 shown in FIG. 1. Table 1 shows the relation betweenthe pull-in mode and the PLL pull-in selection bits PP0 and PP1 of thecontrol register CRG, and Table 2 shows the relation between the on-offcontrol signal for the switches SW3 to SW8 and the pulse widthdesignation bits TP0 to TP2. In accordance with the states of thesebits, the mode control circuit 290 controls the operation mode and pulsewidth of the charge pump.

The mode 2 may be selected by changing the resistor as shown in FIG. 8,instead of changing the current sources to I3 and a×I3. In this case,the resistors R2, R3, . . . are selected by the pulse width designationbits TP0 to TP2 to change the initial voltage at the PLL start-up. Inthis embodiment, although one of the four pull-in modes shown in Table 1is selected, five or more pull-in modes may be used, for example, addinga pull-in mode by changing the resistor such as shown in FIG. 8 andother pull-in modes. TABLE 1 CURRENT PP BITS MODE CONTROL STATE SOURCESFIGURE 0 0 MODE 0 NORMAL LOCK I3 0 1 MODE 1 DOWN-SWEEP I4, I8 1 0 MODE 2UP-SWEEP I3, I5(aI3) HIGH SPEED 1 1 1 MODE 3 UP-SWEEP I3, I5, I6, I7HIGH SPEED 2

TABLE 2 TP BITS PULSE WIDTH 000  0 μsec 001  5 μsec 010 10 μsec 011 15μsec 100 20 μsec 101 25 μsec 110 30 μsec 111 35 μsec

In the high frequency LSI of this embodiment, the transmission side PLLhas a plurality of pull-in modes. It is therefore possible to change thepull-in mode in accordance with the frequency band used by a multi bandwireless communication system or in accordance with the applied system.The lock-in state can therefore be obtained in a short time after thePLL start-up. If the down-sweep high speed lock-up of the mode 1 is notused, the high speed lock-up becomes possible while the image lock at anundesired frequency is reliably avoided. There may be a system whichuses a high frequency LSI having a down-sweep high speed lock-up modeand can avoid the image lock by devising a system control program or thelike. If the high frequency LSI of the embodiment is used as the highfrequency LSI of such a system and the down-sweep high speed lock-upmode of the mode 1 is selected, it is possible to configure the systemcapable of avoiding the image lock by utilizing conventional resources.

Next, a method of setting a frequency of an oscillator, particularly anoscillator for generating an oscillation signal of an intermediatefrequency, will be described with reference to Table 3 to Table 5 andFIG. 8. In the following description, the embodiment is applied to ahigh frequency LSI of a triple band type mobile communication systemcapable of processing three signals in the GSM frequency band from 880to 915 MHz, DCS frequency band from 1710 to 1785 MHz, and PCS frequencyband from 1850 to 1910 MHz. TABLE 3 RXVCO (MHz) IFVCO TXIF TXVCO TRANS-(MHz) (MHz) (MHz) RECEPTION MISSION GSM900 360 45  880 3700 3700 360 45 915 3840 3840 DCS1800 380 95 1710 3610 3610 380 95 1785 3760 3760

Table 3 shows an example of setting the frequencies of oscillationsignals φIF, φTX and φRF of the intermediate frequency oscillator IFVCO210, transmission oscillator TXVCO 130 and high frequency oscillatorRFVCO 150 of a high frequency LSI of a dual band type capable ofprocessing signals in conventional two GSM and DCS frequency bands. Asshown in Table 3, according to the conventional techniques, theoscillation frequency of the intermediate oscillator IFVCO 210 is set to360 MHz for GSM and to 380 MHz for DCS. These frequencies are thenfrequency-divided at the frequency dividing circuit 220 by ⅛ into 45 MHzof the carrier TXIF for GSM, and by ¼ into 95 MHz of the carrier TXIFfor DCS, the carrier being modulated thereafter.

The oscillation frequency of the high frequency oscillator RFVCO 150 isset to 3700 to 3840 MHz for GAM and to 3610 to 3760 MHz for DCS. Thesefrequencies are then frequency-divided at the frequency dividing circuit250 by ¼ for GSM and by ½ for DCS to obtain φRF′ which is supplied tothe mixer 260. The mixer 260 outputs a difference signal correspondingto a difference (FRF−FTX) between φRF′ and the transmission oscillationsignal φTX supplied from the transmission oscillator 130. PLL operatesto make the difference signal frequency be equal to the modulated signalfrequency FTXIF.

Table 4 shows an example of setting the frequencies of oscillationsignals of oscillators of a high frequency LSI of a triple band typecapable of processing signals in GSM and DCS and PCS. This setting isperformed in a similar manner to a conventional example of setting theoscillation frequencies φIF, φTX and φRF of the intermediate frequencyoscillator IFVCO 210, transmission oscillator TXVCO 130 and highfrequency oscillator RFVCO 150 of a high frequency LSI of a dual bandtype capable of processing signals in conventional two GSM and DCSfrequency bands. TABLE 4 RXVCO (MHz) IFVCO TXIF TXVCO TRANS- (MHz) (MHz)(MHz) RECEPTION MISSION GSM900 360 45  880 3700 3700 360 45  915 38403840 DCS1800 380 95 1710 3610 3610 380 95 1785 3760 3760 PCS1900 320 801850 3860 3860 320 80 1910 3980 3980

As seen from Table 4, if the frequency of each oscillator is set in asimilar manner to the conventional example, for PCS, the oscillationfrequency of the intermediate frequency oscillator IFVCO 210 is set to320 MHz which is frequency-divided at the frequency dividing circuit 220by ¼ to generate the carrier TXIF of 80 MHz to be modulated. For PCS,the oscillation frequency of the high frequency oscillator RFVCO 150 isset to 3860 to 3980 MHz which is frequency-divided at the frequencydividing circuit 250 by ½ to be supplied to the mixer 260. It istherefore necessary for the oscillation frequency of the intermediatefrequency oscillator IFVCO 210 to be set in the range from 320 to 380MHz corresponding to the frequency band to be used. Namely, there is achange width of about 15 to 18%.

It is difficult to form an oscillator capable of oscillating at acorrect oscillation frequency in such a large width. From this reason,three oscillators for three frequency bands are selectively used. Ifthree frequencies of the intermediate frequency signals are used, inorder to cut these harmonic components, three harmonic filters 241 andthree harmonic filters 242 are required to be placed between themodulator circuit 230 and phase detecting circuit 270 and between themixer 260 and phase detecting circuit 270 shown in FIG. 7. Thisincreases the circuit area and chip size. From this reason, it isdifficult to form one chip high frequency LSI of a triple band type.

Table 5 shows an example of setting the frequencies of oscillationsignals φIF, φTX and φRF of the intermediate frequency oscillator IFVCO210, transmission oscillator TXVCO 130 and high frequency oscillatorRFVCO 150 of a high frequency LSI of a triple band type according to theembodiment. TABLE 5 RXVCO (MHz) IFVCO TXIF TXVCO TRANS- (MHz) (MHz)(MHz) RECEPTION MISSION GSM900 640 80  880 3700 3840 640 80  915 38403980 DCS1800 640 80 1710 3610 3580 640 80 1785 3760 3730 PCS1900 640 801850 3860 3860 640 80 1910 3980 3980

As shown in Table 5, in this embodiment, the oscillation frequency ofthe intermediate frequency oscillator IFVCO 210 is set to 640 MHz forall GSM, DCS and PCS which is then frequency-divided at the frequencydividing circuit 220 by ⅛ to generate the carrier TXIF of 80 MHz to bemodulated.

The oscillation frequency of the high frequency oscillator RFVCO 150 isset to 3840 to 3980 MHz for GSM, to 3580 to 3730 MHz for DCS, and to3860 to 3980 MHz for PCS. These frequencies are frequency-divided at thefrequency dividing circuit 250 by ¼ for GSM and by ½ for DCS and PCS togenerate φRF′ and supply it to the mixer 260. The mixer 260 outputs adifference signal corresponding to a difference (FRF−FTX) between φRF′and the transmission oscillation signal φTX supplied from thetransmission oscillator 130. The transmission PLL (TXPLL) operates tomake the difference signal frequency be equal to the modulated signalfrequency FTXIF.

As understood from the comparison between Tables 4 and 5, theoscillation frequency of the intermediate frequency oscillator IFVCO 210is set to 640 MHz for all GSM, DCS and PCS. Therefore, although threeoscillators are necessary if the conventional design techniques areused, only one oscillator is used in this embodiment. Since only oneintermediate frequency oscillator IFVCO 210 is used, only one harmonicfilter 241 and only one harmonic filer 242 are provided between themodulator circuit 230 and phase detecting circuit 270 and between themixer 260 and phase detecting circuit 270 as shown in FIG. 8.

It is therefore possible to considerably reduce the circuit area ascompared to the conventional techniques. It is also possible to form theintermediate frequency oscillator IFVCO 210 excepting the capacitorelement (if a Colpitts oscillator circuit using an LC resonance circuitis used, an inductor element and a varicap diode are included) on asemiconductor chip and to form one chip high frequency LSI. The numberof components of a mobile communication apparatus such as a portablephone can therefore be reduced and the apparatus can be made compact.

As understood from the comparison between Tables 4 and 5, in thisembodiment, the oscillation frequency range of the high frequencyoscillator RFVCO 150 increases to 3580 to 3980 MHz from the conventionalmaximum change range from 3610 to 3840 MHz. It is necessary to increasethe oscillation frequency range of the high frequency oscillator RFVCO150 more than the conventional range. However, this change width is onlyabout 10% and the design is easier than the conventional case that theoscillation frequency change width of the intermediate frequencyoscillator IFVCO 210 is broadened (as described earlier, about 15 to18%).

In this embodiment, although the oscillation frequency of theintermediate frequency oscillator IFVCO 210 is set to 640 MHz and thefrequency of the carrier TXIF is set to 80 MHz, these frequencies arenot limited only thereto, but the integer multiplication of thesefrequencies may also be used. For example, even if the frequency of thecarrier TXIF is doubled to 160 MHz, the circuit operates normally.However, the consumption power at the 80 MHz is smaller than that at 160MHz. This embodiment is applied to a high frequency LSI of the tripleband type capable of processing three signals in GSM, DCS and PCSfrequency bands so that frequency of the carrier TXIF is set to 80 MHz.It is obvious that for a high frequency LSI processing a signal ofanother frequency band, a frequency suitable for this LSI is set.

The invention made by the present inventors has been describedspecifically in connection with the embodiments. The invention is notlimited only to those embodiments. For example, although the embodimentsare applied to a high frequency LSI of the triple band type capable ofprocessing three signals in GSM, DCS and PCS frequency bands, theembodiments may be applied to a high frequency LSI of a dual band typecapable of processing two signals among two of GSM, DCS and PCS.

In the foregoing description, the invention made by the presentinventors is applied to a PLL circuit used by a wireless communicationsystem such as a portable phone in the application field of thebackground of the invention. The invention is not limited only thereto,but the invention is broadly applicable to a semiconductor integratedcircuit device with a PLL circuit, particularly to a generalsemiconductor integrated circuit device with a PLL circuit whoseoperation is temporarily stopped.

According to the embodiments of the invention, the pull-in operation isperformed in the pull-in mode suitable for the frequency band so thatthe lock-up can be realized in a short time without an image lock. Sincethe semiconductor integrated circuit device has a PLL circuit capable ofperforming a pull-in operation by selecting the pull-in mode suitablefor the system, conventional design resources can be used as they are.

A method of setting the frequency of an intermediate frequency signal isprovided, which frequency is optimum to the high frequency LSI capableof communications by a plurality of communication methods such as GSM,DCS and PCS. Accordingly, the main circuit portion of the oscillatorcircuit for generating an intermediate frequency signal can be formed onone semiconductor chip. The number of necessary filters is small so thatthe circuit area can be reduced.

1. A communication semiconductor integrated circuit device with a PLLcircuit having a phase detecting circuit for detecting a phasedifference between a signal having a predetermined frequency and afeedback signal, a charge pump and a filter capacitor for generating avoltage corresponding to the phase difference detected by the phasedetecting circuit, and an oscillator circuit for performing anoscillation operation in accordance with the voltage across the filtercapacitor, wherein÷ the PLL circuit has a plurality of pull-in operationmodes for pulling the voltage across the filter capacitor in a lock-upvoltage in response to an activation of the PLL circuit, and performsthe pull-in operation in accordance with a setting value in a firstregister for designating one of the plurality of pull-in operationmodes.
 2. A communication semiconductor integrated circuit deviceaccording to claim 1, wherein at last one of the plurality of pull-inoperation modes is an operation mode of starting the pull-in operationat a predetermined initial voltage lower than the lock-up voltage.
 3. Acommunication semiconductor integrated circuit device according to claim2, wherein at last one of the plurality of pull-in operation modes is anoperation mode of raising the voltage across the filter capacitor to apredetermined voltage higher than the lock-up voltage and thereaftergradually lowering the voltage across the filter capacitor.
 4. Acommunication semiconductor integrated circuit device according to claim2, wherein the PLL circuit can select one of a plurality of levels asthe initial voltage and has a second register for designating one of theplurality of levels.
 5. A communication semiconductor integrated circuitdevice according to claim 4, wherein a first current source for chargingup the voltage across the filter capacitor at a start-up time and asecond current source for charging up the voltage across the filtercapacitor are provided, the second current source flows a current largerthan a current flowing from the first current source, a time duringwhich the second current source charges up the voltage across the filtercapacitor is changed with a setting value in the second register.
 6. Acommunication semiconductor integrated circuit device according to claim1, wherein the signal having the predetermined frequency is a modulatedsignal obtained by modulating a signal having a first frequency bytransmission data, and the feedback signal is a signal which is outputfrom a mixer for synthesizing an oscillation signal of the oscillatorcircuit and a signal having a second frequency higher than the firstfrequency and which has a frequency equal to a difference between afrequency of the oscillation signal and the frequency of the signalhaving the second frequency.
 7. A wireless communication system capableof transmission/reception in conformity with a communication methodusing two or more frequency bands including at least a GSM method usinga 900 MHz frequency band, wherein a same frequency of an intermediatefrequency signal to be modulated by transmission data is used for thetwo or more frequency bands.
 8. A wireless communication systemaccording to claim 7, wherein the communication method using the two ormore frequency bands includes the GSM method in a 900 MHz frequencyband, a DCS method in a 1800 MHz frequency band, and a PCS method in a1900 MHz frequency band.
 9. A wireless communication system according toclaim 7, wherein the frequency of the intermediate frequency signal is80 MHz.
 10. A wireless communication system according to claim 7,wherein an oscillator circuit for generating the intermediate frequencysignal is a Colpitts oscillator circuit, and constituent elements of theoscillator circuit excepting a capacitor element constituting an LCresonance circuit are formed on the same semiconductor chip as that of amodulation circuit for modulating the intermediate frequency signal bytransmission data.